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low voltage, 1.15 v to 5.5 v, 8-channel bidirectional logic level translators adg3308/ADG3308-1 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2007 analog devices, inc. all rights reserved. features bidirectional logic level translation operates from 1.15 v to 5.5 v low quiescent current < 1 a no direction pin applications low voltage asic level translation smart card readers cell phones and cell phone cradles portable communication devices telecommunications equipment network switches and routers storage systems (san/nas) computing/server applications gps portable pos systems low cost serial interfaces functional block diagram a1 y1 gnd v ccy v cca a8 y8 a7 y7 a6 y6 a5 y5 a4 y4 a3 y3 a2 y2 en adg3308/ADG3308-1/ adg3308-2 0 4865-001 figure 1. general description the adg3308/ADG3308-1/adg3308-2 are bidirectional level translators containing eight bidirectional channels. they can be used in multivoltage digital system applications, such as a data transfer between a low voltage dsp controller and a higher voltage device. the internal architecture allows the device to perform bidirectional level translation without an additional signal to set the direction in which the translation takes place. the voltage applied to v cca sets the logic levels on the a side of the device, and v ccy sets the levels on the y side. for proper operation, v cca must always be less than v ccy . the v cca compatible logic signals applied to the a side of the device appear as v ccy compatible levels on the y side. similarly, v ccy compatible logic levels applied to the y side of the device appear as v cca compatible logic levels on the a side. the enable pin (en) provides three-state operation on both the a side and the y side pins. when the en pin is pulled low, the terminals on both sides of the device are in the high impedance state. for normal operation, en should be driven high. the adg3308 is available in a compact 20-lead tssop and a 20-lead lfcsp, the ADG3308-1 is available in a 20-ball wlcsp, and the adg3308-2 is available in a backside-coated 20-ball wlcsp. the en pin is referred to the v ccy supply voltage for the adg3308 and to the v cca supply voltage for the ADG3308-1 and adg3308-2. the adg3308/ADG3308-1/adg3308-2 are guaranteed to operate over the 1.15 v to 5.5 v supply voltage range and the extended ?40c to +85c temperature range. product highlights 1. bidirectional logic level translation. 2. fully guaranteed over the 1.15 v to 5.5 v supply range. 3. no direction pin. 4. packages: 20-lead tssop and 20-lead lfcsp (adg3308), 20-ball wlcsp (ADG3308-1), and backside-coated 20-ball wlcsp (adg3308-2).
adg3308/ADG3308-1 rev. c | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 test circ u its ..................................................................................... 12 ter mi nolo g y .................................................................................... 15 theory of operation ...................................................................... 16 level translator architecture ................................................... 16 input driving requirements ..................................................... 16 output load requirements ...................................................... 16 enable operation ....................................................................... 16 power supplies ............................................................................ 16 data rate ..................................................................................... 17 applications ..................................................................................... 18 layout guidelines ....................................................................... 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 20 revision history 9 /07rev. b to rev. c updated outline dimensions ....................................................... 19 7/07rev. a to rev. b added backside-coated wlcsp package ......................universal changes to input driving requirements section ...................... 16 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 7/06rev. 0 to rev. a added wlcsp package..universal added figure 4......7 updated outline dimensions.19 changes to ordering gu ide ....19 1/05revision 0: initial version
adg3308/ADG3308-1 rev. c | page 3 of 20 specifications v ccy = 1.65 v to 5.5 v, v cca = 1.15 v to v ccy , gnd = 0 v. all specifications t min to t max , unless otherwise noted. 1 table 1. parameter symbol conditions min typ 2 max unit logic inputs/outputs a side input high voltage 3 v iha v cca = 1.15 v v cca ? 0.3 v v iha v cca = 1.2 v to 5.5 v 0.65 v cca v input low voltage 3 v ila 0.35 v cca v output high voltage v oha v y = v ccy , i oh = 20 a, see figure 29 v cca ? 0.4 v output low voltage v ola v y = 0 v, i ol = 20 a, see figure 29 0.4 v capacitance 3 c a f = 1 mhz, en = 0, see figure 34 10 pf leakage current i la, high-z v a = 0 v or v cca , en = 0, see figure 31 1 a y side input high voltage 3 v ihy 0.65 v ccy v input low voltage 3 v ily 0.35 v ccy v output high voltage v ohy v a = v cca , i oh = 20 a, see figure 30 v ccy ? 0.4 v output low voltage v oly v a = 0 v, i ol = 20 a, see figure 30 0.4 v capacitance 3 c y f = 1 mhz, en = 0, see figure 35 6.8 pf leakage current i ly, high-z v y = 0 v or v ccy , en = 0, see figure 32 1 a enable (en) input high voltage 3 v ihen adg3308 (tssop, lfcsp) 0.65 v ccy v ADG3308-1/adg3308-2 (wlcsp) v cca = 1.15 v v cca ? 0.3 v v cca = 1.2 v to 5.5 v 0.65 v cca v input low voltage 3 v ilen adg3308 (tssop, lfcsp) 0.35 v ccy v ADG3308-1/adg3308-2 (wlcsp) 0.35 v cca v leakage current i len v en = 0 v or v ccy , v a = 0 v, see figure 33 1 a capacitance 3 c en 4.5 pf enable time 3 t en r s = r t = 50 , v a = 0 v or v cca (a y), v y = 0 v or v ccy (y a), see figure 36 1 1.8 s switching characteristics 3 3.3 v 0.3 v v cca v ccy , v ccy = 5 v 0.5 v a y level translation r s = r t = 50 , c l = 50 pf, see figure 37 propagation delay t p, a y 6 10 ns rise time t r, ay 2 3.5 ns fall time t f, a y 2 3.5 ns maximum data rate d max, a y 50 mbps channel-to-channel skew t skew, a y 2 4 ns part-to-part skew t ppskew, a y 3 ns y a level translation r s = r t = 50 , c l = 15 pf, see figure 38 propagation delay t p, y a 4 7 ns rise time t r, y a 1 3 ns fall time t f, y a 3 7 ns maximum data rate d max, y a 50 mbps channel-to-channel skew t skew, y a 2 3.5 ns part-to-part skew t ppskew, y a 2 ns
adg3308/ADG3308-1 rev. c | page 4 of 20 parameter symbol conditions min typ 2 max unit 1.8 v 0.15 v v cca v ccy , v ccy = 3.3 v 0.3 v a y level translation r s = r t = 50 , c l = 50 pf, see figure 37 propagation delay t p, a y 8 11 ns rise time t r, ay 2 5 ns fall time t f, a y 2 5 ns maximum data rate d max, a y 50 mbps channel-to-channel skew t skew, a y 2 4 ns part-to-part skew t ppskew, a y 4 ns y a level translation r s = r t = 50 , c l = 15 pf, see figure 38 propagation delay t p, y a 5 8 ns rise time t r, y a 2 3.5 ns fall time t f, y a 2 3.5 ns maximum data rate d max, y a 50 mbps channel-to-channel skew t skew, y a 2 3 ns part-to-part skew t ppskew, y a 3 ns 1.15 v to 1.3 v v cca v ccy , v ccy = 3.3 v 0.3 v a y level translation r s = r t = 50 , c l = 50 pf, see figure 37 propagation delay t p, a y 9 18 ns rise time t r, ay 3 5 ns fall time t f, a y 2 5 ns maximum data rate d max, a y 40 mbps channel-to-channel skew t skew, a y 2 5 ns part-to-part skew t ppskew, a y 10 ns y a level translation r s = r t = 50 , c l = 15 pf, see figure 38 propagation delay t p, y a 5 9 ns rise time t r, y a 2 4 ns fall time t f, y a 2 4 ns maximum data rate d max, y a 40 mbps channel-to-channel skew t skew, y a 2 4 ns part-to-part skew t ppskew, y a 4 ns 1.15 v to 1.3 v v cca v ccy , v ccy = 1.8 v 0.3 v a y level translation r s = r t = 50 , c l = 50 pf, see figure 37 propagation delay t p, a y 12 25 ns rise time t r, ay 7 12 ns fall time t f, a y 3 5 ns maximum data rate d max, a y 25 mbps channel-to-channel skew t skew, a y 2 5 ns part-to-part skew t ppskew, a y 15 ns y a level translation r s = r t = 50 , c l = 15 pf, see figure 38 propagation delay t p, y a 14 35 ns rise time t r, y a 5 16 ns fall time t f, y a 2.5 6.5 ns maximum data rate d max, y a 25 mbps channel-to-channel skew t skew, y a 3 6.5 ns part-to-part skew t ppskew, y a 23.5 ns
adg3308/ADG3308-1 rev. c | page 5 of 20 parameter symbol conditions min typ 2 max unit 2.5 v 0.2 v v cca v ccy , v ccy = 3.3 v 0.3 v a y level translation r s = r t = 50 , c l = 50 pf, see figure 37 propagation delay t p, a y 7 10 ns rise time t r, ay 2.5 4 ns fall time t f, a y 2 5 ns maximum data rate d max, a y 60 mbps channel-to-channel skew t skew, a y 1.5 2 ns part-to-part skew t ppskew, a y 4 ns y a level translation r s = r t = 50 , c l = 15 pf, see figure 38 propagation delay t p, y a 5 8 ns rise time t r, y a 1 4 ns fall time t f, y a 3 5 ns maximum data rate d max, y a 60 mbps channel-to-channel skew t skew, y a 2 3 ns part-to-part skew t ppskew, y a 3 ns power requirements power supply voltages v cca v cca v ccy 1.15 5.5 v v ccy 1.65 5.5 v quiescent power supply current i cca v a = 0 v or v cca , v y = 0 v or v ccy , v cca = v ccy = 5.5 v, en = v ccy 0.17 1 a i ccy v a = 0 v or v cca , v y = 0 v or v ccy , v cca = v ccy = 5.5 v, en = v ccy 0.27 1 a three-state mode power supply current i high-za v cca = v ccy = 5.5 v, en = 0 0.1 1 a i high-zy v cca = v ccy = 5.5 v, en = 0 0.1 1 a 1 temperature range is ?40c to +85c (b version) for the tssop, the lfcsp, the wlcsp, and the backside-coated wlcsp. 2 all typical values are at t a = 25c, unless otherwise noted. 3 guaranteed by design; not subject to production test.
adg3308/ADG3308-1 rev. c | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 2. parameter rating v cca to gnd ?0.3 v to +7 v v ccy to gnd v cca to +7 v digital inputs (a) ?0.3 v to (v cca + 0.3 v) digital inputs (y) ?0.3 v to (v ccy + 0.3 v) en to gnd ?0.3 v to +7 v operating temperature range extended industrial range (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 20-lead tssop 78c/w 20-lead lfcsp 30.4c/w 20-ball wlcsp 100c/w 20-ball backside-coated wlcsp 100c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 260c (+0c/?5c) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution
adg3308/ADG3308-1 rev. c | page 7 of 20 pin configurations and function descriptions y8 gnd y7 en v cca a1 a2 a5 a6 y6 v ccy a7 a8 y1 y2 y3 y4 y5 a3 a4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 adg3308 top view (not to scale) 0 4865-002 04865-003 a2 a3 a4 a5 a6 pin 1 indicator 1 2 3 4 5 13 y5 14 y4 15 y3 12 y6 11 y7 6 a 7 7 a 8 8 e n 1 0 y 8 9 g n d 1 8 v c c y 1 9 v c c a 2 0 a 1 1 7 y 1 1 6 y 2 top view (not to scale) adg3308 t he exposed pad can be tied to g nd or it can be left floating. do not tie it to v cca or v ccy . ADG3308-1/ adg3308-2 top view (not to scale) (balls at the bottom) ball a1 indicator y1 a1 v cca 1234 y3 a3 a2 y5 a5 a4 y7 a7 a6 v ccy y2 y4 y6 y8 a b c d e gnd en a8 04865-057 figure 2. 20-lead tssop figure 3. 20- lead lfcsp figure 4. 20-ball wlcsp table 3. pin function descriptions pin/ball no. tssop lfcsp wlcsp mnemonic description 1 19 a4 v cca power supply. power supply voltage input for the a1 i/o pin to the a8 i/o pin (1.15 v v cca < v ccy ). 2 20 a3 a1 input/output a1. referenced to v cca . 3 1 b4 a2 input/output a2. referenced to v cca . 4 2 b3 a3 input/output a3. referenced to v cca . 5 3 c4 a4 input/output a4. referenced to v cca . 6 4 c3 a5 input/output a5. referenced to v cca . 7 5 d4 a6 input/output a6. referenced to v cca . 8 6 d3 a7 input/output a7. referenced to v cca . 9 7 e4 a8 input/output a8. referenced to v cca . 10 8 e3 en active high enable input. 11 9 e2 gnd ground. 12 10 e1 y8 input/output y8. referenced to v ccy . 13 11 d2 y7 input/output y7. referenced to v ccy . 14 12 d1 y6 input/output y6. referenced to v ccy . 15 13 c2 y5 input/output y5. referenced to v ccy . 16 14 c1 y4 input/output y4. referenced to v ccy . 17 15 b2 y3 input/output y3. referenced to v ccy . 18 16 b1 y2 input/output y2. referenced to v ccy . 19 17 a2 y1 input/output y1. referenced to v ccy . 20 18 a1 v ccy power supply. power supply voltage input for the y1 i/o pin to the y8 i/o pin (1.65 v v ccy 5.5 v).
adg3308/ADG3308-1 rev. c | page 8 of 20 typical performance characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) t a = 25c 1 channel c l = 50pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v i cca (ma) 04865-004 figure 5. i cca vs. data rate (a y level translation) 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) t a = 25c 1 channel c l = 50pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v i ccy (ma) 04865-005 figure 6. i ccy vs. data rate (a y level translation) 0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) i cca (ma) t a = 25c 1 channel c l = 15pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v 04865-006 figure 7. i cca vs. data rate (y a level translation) 0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) i ccy (ma) t a = 25c 1 channel c l = 15pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v 04865-007 figure 8. i ccy vs. data rate (y a level translation) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 13 23 33 43 53 63 73 capacitive load (pf) i ccy (ma) 20mbps 10mbps 5mbps 1mbps t a = 25c 1 channel v cca = 1.2v v ccy = 1.8v 04865-012 figure 9. i ccy vs. capacitive load at pin y for a y (1.2 v 1.8 v) level translation 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 13 23 33 43 53 capacitive load (pf) i cca (ma) 20mbps 10mbps 5mbps 1mbps t a = 25c 1 channel v cca = 1.2v v ccy = 1.8v 0 4865-013 figure 10. i cca vs. capacitive load at pin a for y a (1.8 v 1.2 v) level translation
adg3308/ADG3308-1 rev. c | page 9 of 20 0 1 2 3 4 5 6 7 8 9 i ccy (ma) 13 23 33 43 53 63 73 capacitive load (pf) t a =25c 1 channel v cca = 1.8v v ccy = 3.3v 30mbps 20mbps 10mbps 5mbps 50mbps 04865-016 figure 11. i ccy vs. capacitive load at pin y for a y (1.8 v 3.3 v) level translation 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 i cca (ma) 13 23 33 43 53 capacitive load (pf) 50mbps t a = 25c 1 channel v cca = 1.8v v ccy = 3.3v 5mbps 10mbps 20mbps 30mbps 04865-017 figure 12. i cca vs. capacitive load at pin a for y a (3.3 v 1.8 v) level translation 0 2 4 6 8 10 12 i ccy (ma) 13 23 33 43 53 63 73 capacitive load (pf) t a = 25c 1 channel v cca = 3.3v v ccy = 5v 50mbps 30mbps 20mbps 10mbps 5mbps 04865-020 figure 13. i ccy vs. capacitive load at pin y for a y (3.3 v 5 v) level translation 0 2 4 6 i cca (ma) 13 23 33 43 53 capacitive load (pf) t a =25c 1 channel v cca = 3.3v v ccy = 5v 50mbps 20mbps 10mbps 5mbps 1 3 5 7 0 4865-021 30mbps figure 14. i cca vs. capacitive load at pin a for y a (5 v 3.3 v) level translation 0 1 2 3 4 5 6 7 8 9 10 13 23 33 43 53 63 73 capacitive load (pf) rise time (ns) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 04865-023 figure 15. rise time vs. capacitive load at pin y (a y level translation) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 13 23 33 43 53 63 73 capacitive load (pf) fall time (ns) t a = 25c 1 channel data rate = 50kbps v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v v cca = 1.2v, v ccy = 1.8v 04865-024 figure 16. fall time vs. capacitive load at pin y (a y level translation)
adg3308/ADG3308-1 rev. c | page 10 of 20 0 1 2 3 4 5 6 7 8 9 10 13 18 23 28 33 38 43 48 53 rise time (ns) capacitive load (pf) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 0 4865-025 figure 17. rise time vs. capacitive load at pin a (y a level translation) 13 18 23 28 33 38 43 48 53 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fall time (ns) capacitive load (pf) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 04865-026 figure 18. fall time vs. capacitive load at pin a (y a level translation) 0 2 4 6 8 10 12 14 13 23 33 43 53 63 73 capacitive load (pf) propagation delay (ns) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 0 4865-027 figure 19. propagation delay (t plh ) vs. capacitive load at pin y (a y level translation) 0 2 4 6 8 10 12 13 23 33 43 53 63 73 propagation delay (ns) capacitive load (pf) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 04865-028 figure 20. propagation delay (t phl ) vs. capacitive load at pin y (a y level translation) 0 1 2 3 4 5 6 7 8 9 13 18 23 28 33 38 43 48 53 capacitive load (pf) propagation delay (ns) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 04865-029 figure 21. propagation delay (t plh ) vs. capacitive load at pin a (y a level translation) 0 1 2 3 4 5 6 7 8 9 13 18 23 28 33 38 43 48 53 capacitive load (pf) propagation delay (ns) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 04865-030 figure 22. propagation delay (t phl ) vs. capacitive load at pin a (y a level translation)
adg3308/ADG3308-1 rev. c | page 11 of 20 t a = 25c data rate = 25mbps c l = 50pf 1 channel 5ns/div 400mv/div 04865-037 figure 23. eye diagram at y output (1.2 v 1.8 v level translation, 25 mbps) 5ns/div 200mv/div t a = 25c data rate = 25mbps c l = 50pf 1 channel 04865-038 figure 24. eye diagram at a output (1.8 v 1.2 v level translation, 25 mbps) t a = 25c data rate = 50mbps 3ns/div 500mv/div c l = 50pf 1 channel 04865-039 figure 25. eye diagram at y output (1.8 v 3.3 v level translation, 50 mbps) t a = 25c data rate = 50mbps c l = 15pf 1 channel 3ns/div 400mv/div 04865-040 figure 26. eye diagram at a output (3.3 v 1.8 v level translation, 50 mbps) t a = 25c data rate = 50mbps c l = 50pf 1 channel 3ns/div 1v/div 04865-041 figure 27. eye diagram at y output (3.3 v 5 v level translation, 50 mbps) t a = 25c data rate = 50mbps c l = 15pf 1 channel 3ns/div 800mv/div 04865-042 figure 28. eye diagram at a output (5 v 3.3 v level translation, 50 mbps)
adg3308/ADG3308-1 rev. c | page 12 of 20 test circuits adg3308/ ADG3308-1 / adg3308-2 ax yx gnd v cca v ccy en k1 k2 i oh i ol 0.1f 0.1f 04865-043 figure 29. v oh /v ol voltages at pin a adg3308/ ADG3308-1 / adg3308-2 yx xa gnd v ccy v cca en k1 k2 i oh i ol 0.1f 0.1f 04865-044 figure 30. v oh /v ol voltages at pin y adg3308/ ADG3308-1 / adg3308-2 ax yx gnd v cca v ccy k 0.1f 0.1f a en 04865-045 figure 31. three-state leakage current at pin a adg3308/ ADG3308-1 / adg3308-2 ax yx gnd v cca v ccy k 0.1f 0.1f en a 04865-046 figure 32. three-state leakage current at pin y adg3308/ ADG3308-1 / adg3308-2 ax yx gnd v cca v ccy k 0.1f 0.1f en a 04865-047 figure 33. en pin leakage current adg3308/ ADG3308-1 / adg3308-2 ax yx gnd v cca v ccy en capacitance meter 04865-048 figure 34. capacitance at pin a adg3308/ ADG3308-1 / adg3308-2 ax yx gnd v cca v ccy en capacitance meter 04865-049 figure 35. capacitance at pin y
adg3308/ADG3308-1 rev. c | page 13 of 20 90% v en v y /v a t en1 v a /v y v ccy 0v v cca /v ccy 0v v ccy /v cca 0v 10% v en v y /v a t en2 v a /v y v ccy 0v 0v v ccy /v cca 0v signal source v en r t 50? 1m ? v a 15pf adg3308/ ADG3308-1 / adg3308-2 en gnd r s 50? 0.1f 1m ? v cca ax v y v ccy xy k2 z 0 = 50 ? k1 10f + 0.1f 10f + y a direction signal source v en r t 50? v a adg3308/ ADG3308-1 / adg3308-2 en gnd r s 50? 0.1f v cca ax 1m ? v y 50pf 1m ? v ccy xy k2 z 0 = 50 ? k1 10f + 0.1f 10f + a y direction v cca /v ccy notes 1. t en is whichever is larger between t en1 and t en2 in both a y and y a directions. 04865-050 figure 36. enable time
adg3308/ADG3308-1 rev. c | page 14 of 20 50% 50% 10% 90% v a v y t f, a y t r, a y t p, a y t p, a y adg3308/ ADG3308-1 / adg3308-2 gnd signal source v a r t 50 ? r s 50? en v cca v ccy v y 50pf z 0 = 50 ? xy xa 0.1f 10f + 0.1f 10f + 04865-051 figure 37. switching characteristics (a y level translation) 50% 50% 10% 90% v y v a t f, y a t r, y a t p, y a t p, y a adg3308/ ADG3308-1 / adg3308-2 gnd signal source v y r t 50? r s 50 ? en v cca v ccy v a 15pf z 0 = 50 ? xy xa 0.1f 10f + 0.1f 10f + 04865-052 figure 38. switching characteristics (y a level translation)
adg3308/ADG3308-1 rev. c | page 15 of 20 terminology v iha logic input high voltage at pin a1 to pin a8. v ila logic input low voltage at pin a1 to pin a8. v oha logic output high voltage at pin a1 to pin a8. v ola logic output low voltage at pin a1 to pin a8. c a capacitance measured at pin a1 to pin a8 (en = 0). i la, high-z leakage current at pin a1 to pin a8 when en = 0 (high impedance state at pin a1 to pin a8). v ihy logic input high voltage at pin y1 to pin y8. v ily logic input low voltage at pin y1 to pin y8. v ohy logic output high voltage at pin y1 to pin y8. v oly logic output low voltage at pin y1 to pin y8. c y capacitance measured at pin y1 to pin y8 (en = 0). i ly, high-z leakage current at pin y1 to pin y8 when en = 0 (high impedance state at pin y1 to pin y8). v ihen logic input high voltage at the en pin. v ilen logic input low voltage at the en pin. c en capacitance measured at en pin. i len enable (en) pin leakage current. t en three-state enable time for pin a1 to pin a8/pin y1 to pin y8. t p, a y propagation delay when translating logic levels in the ay direction. t r, ay rise time when translating logic levels in the ay direction. t f, ay fall time when translating logic levels in the ay direction. d max, ay guaranteed data rate when translating logic levels in the ay direction under the driving and loading conditions specified in table 1 . t skew, ay difference between propagation delays on any two channels when translating logic levels in the ay direction. t ppskew, ay difference in propagation delay between any one channel and the same channel on a different part (under same driving/ loading conditions) when translating in the ay direction. t p, y a propagation delay when translating logic levels in the ya direction. t r, ya rise time when translating logic levels in the ya direction. t f, ya fall time when translating logic levels in the ya direction. d max, ya guaranteed data rate when translating logic levels in the ya direction under the driving and loading conditions specified in table 1 . t skew, ya difference between propagation delays on any two channels when translating logic levels in the ya direction. t ppskew, ya difference in propagation delay between any one channel and the same channel on a different part (under same driving/ loading conditions) when translating in the ya direction. v cca v cca supply voltage. v ccy v ccy supply voltage. i cca v cca supply current. i ccy v ccy supply current. i high-za v cca supply current during three-state mode (en = 0). i high-zy v ccy supply current during three-state mode (en = 0).
adg3308/ADG3308-1 rev. c | page 16 of 20 theory of operation the adg3308/ADG3308-1/adg3308-2 level translators allow the level shifting necessary for data transfer in a system where multiple supply voltages are used. the device requires two supplies, v cca and v ccy (v cca v ccy ). these supplies set the logic levels on each side of the device. when driving the a pins, the device translates the v cca compatible logic levels to v ccy compatible logic levels available at the y pins. similarly, because the device is capable of bidirectional translation, when driving the y pins the v ccy compatible logic levels are translated to the v cca compatible logic levels available at the a pins. when en = 0, the a1 pin to the a8 pin and the y1 pin to the y8 pin are three-stated. when en is driven high, the adg3308/ ADG3308-1/adg3308-2 go into normal operation mode and perform level translation. level translator architecture the adg3308/ADG3308-1/adg3308-2 consist of eight bidirectional channels. each channel can translate logic levels in either the ay or the ya direction. they use a one-shot accelerator architecture, ensuring excellent switching charac- teristics. figure 39 shows a simplified block diagram of a bidirectional channel. one-shot generator 6k? 6k ? y v cca v ccy t2 t1 t3 t4 a p n u1 u2 u4 u3 0 4865-053 figure 39. simplified block diagram of an adg3308/ADG3308-1/adg3308-2 channel the logic level translation in the ay direction is performed using a level translator (u1) and an inverter (u2), whereas the translation in the ya direction is performed using the u3 inverter and u4 inverter. the one-shot generator detects a rising or falling edge present on either the a side or the y side of the channel. it sends a short pulse that turns on the pmos transistors (t1 and t2) for a rising edge, or the nmos transistors (t3 and t4) for a falling edge. this charges/discharges the capacitive load faster, resulting in fast rise and fall times. the inputs of the unused channels (a or y) should be tied to their corresponding v cc rail (v cca or v ccy ) or to gnd. input driving requirements to ensure correct operation of the adg3308/ADG3308-1/ adg3308-2, the circuit that drives the input of the device should be able to ensure rise/fall times of less than 3 ns when driving a load consisting of a 6 k resistor in parallel with the input capacitance of the adg3308/ADG3308-1/adg3308-2 channel. output load requirements the adg3308/ADG3308-1/adg3308-2 level translators are designed to drive cmos-compatible loads. if current-driving capability is required, it is recommended to use buffers between the adg3308/ADG3308-1/adg3308-2 outputs and the load. enable operation the adg3308/ADG3308-1/adg3308-2 provide three-state operation at the a i/o pins and the y i/o pins by using the enable (en) pin, as shown in table 4 . table 4. truth table en y i/o pins a i/o pins 0 high-z 1 high-z 1 1 normal operation 2 normal operation 2 1 high impedance state. 2 in normal operation, the adg 3308/ADG3308-1/adg3308-2 perform level translation. when en = 0, the adg3308/ADG3308-1/adg3308-2 enter into three-state mode. in this mode, the current consumption from both the v cca and v ccy supplies is reduced, allowing the user to save power, which is critical, especially in battery- operated systems. the en input pin can only be driven with v ccy compatible logic levels for the adg3308, whereas the ADG3308-1/adg3308-2 can be driven with either v cca - or v ccy compatible logic levels. power supplies for proper operation of the device, the voltage applied to the v cca must always be less than or equal to the voltage applied to v ccy . to meet this condition, the recommended power-up sequence is v ccy first and then v cca . the adg3308/ADG3308-1/ adg3308-2 operate properly only after both supply voltages reach their nominal values. it is not recommended to use the part in a system where, during power-up, v cca may be greater than v ccy due to a significant increase in the current taken from the v cca supply. for optimum performance, the v cca and v ccy pins should be decoupled to gnd as close as possible to the device.
adg3308/ADG3308-1 rev. c | page 17 of 20 data rate the maximum data rate at which the device is guaranteed to operate is a function of the v cca and v ccy supply voltage combination and the load capacitance. it represents the maximum frequency of a square wave that can be applied to the i/o pins, ensuring that the device operates within the data sheet specifications in terms of output voltage (v ol and v oh ) and power dissipation (the junction temperature does not exceed the value specified under the absolute maximum ratings section). table 5 shows the guaranteed data rates at which the adg3308/ ADG3308-1/adg3308-2 can operate in both directions (ay level translation or ya level translation) for various v cca and v ccy supply combinations. table 5. guaranteed data rates 1 v ccy v cca 1.8 v (1.65 v to 1.95 v) 2.5 v (2.3 v to 2.7 v) 3.3 v (3.0 v to 3.6 v) 5 v (4.5 v to 5.5 v) 1.2 v (1.15 v to 1.3 v) 25 mbps 30 mbps 40 mbps 40 mbps 1.8 v (1.65 v to 1.95 v) 45 mbps 50 mbps 50 mbps 2.5 v (2.3 v to 2.7 v) 60 mbps 50 mbps 3.3 v (3.0 v to 3.6 v) 50 mbps 5 v (4.5 v to 5.5 v) 1 the load capacitance used is 50 pf when translating in the a y direction and 15 pf when translating in the y a direction.
adg3308/ADG3308-1 rev. c | page 18 of 20 applications the adg3308/ADG3308-1/adg3308-2 are designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. the lower voltage logic signals are connected to the a pins, and the higher voltage logic signals to the y pins. the adg3308/ADG3308-1/adg3308-2 can provide level translation in both directions (ay or ya) on all eight channels, eliminating the need for a level translator ic for each direction. the internal architecture allows the adg3308/ ADG3308-1/adg3308-2 to perform bidirectional level translation without an additional signal to set the direction in which the translation is made. it also allows simultaneous data flow in both directions on the same part, for example, when two channels translate in the ay direction while the other two translate in the ya direction. this simplifies the design by eliminating the timing requirements for the direction signal and reduces the number of ics used for level translation. figure 40 shows an application where a 3.3 v microprocessor can read or write data to and from a 1.8 v peripheral device using an 8-bit bus. v cca a1 a2 a3 a4 en gnd y4 y3 y2 y1 v ccy microprocessor/ microcontroller/ dsp 3.3v 1.8v peripheral device 100nf 100nf i/o h 1 i/o h 4 i/o h 3 i/o h 2 i/o l 1 i/o l 4 i/o l 3 i/o l 2 gnd gnd a5 a6 a7 a8 y8 y7 y6 y5 adg3308/ ADG3308-1 / adg3308-2 i/o h 5 i/o h 8 i/o h 7 i/o h 6 i/o l 5 i/o l 8 i/o l 7 i/o l 6 04865-056 figure 40. 1.8 v to 3.3 v 8-bit level translation circuit when the application requires level translation between a microprocessor and multiple peripheral devices, the adg3308/ADG3308-1/adg3308-2 i/o pins can be three- stated by setting en = 0. this feature allows the adg3308/ ADG3308-1/adg3308-2 to share the data buses with other devices without causing contention issues. figure 41 shows an application where a 3.3 v microprocessor is connected to 1.8 v peripheral devices using the three-state feature. adg3308/ ADG3308-1 / adg3308-2 microprocessor/ microcontroller/ dsp i/o h 1 cs 3.3v 1.8v peripheral device 1 peripheral device 2 100nf 100nf i/o h 2 i/o h 8 i/o h 7 i/o h 6 i/o h 5 i/o h 4 i/o h 3 gnd 1.8v 100nf 100nf i/o l 1 i/o l 2 i/o l 8 i/o l 7 i/o l 6 i/o l 5 i/o l 4 i/o l 3 gnd gnd y1 v ccy y2 y3 y4 y5 y6 y7 y8 en gnd a8 a7 a6 a5 a4 a3 a2 a1 v cca adg3308/ ADG3308-1 / adg3308-2 i/o l 1 i/o l 2 i/o l 8 i/o l 7 i/o l 6 i/o l 5 i/o l 4 i/o l 3 y1 v ccy y2 y3 y4 y5 y6 y7 y8 en gnd a8 a7 a6 a5 a4 a3 a2 a1 v cca 04865-055 figure 41. 1.8 v to 3.3 v level translation circuit using the three-state feature layout guidelines as with any high speed digital ic, the printed circuit board layout is important in the overall performance of the circuit. care should be taken to ensure proper power supply bypass and return paths for the high speed signals. each v cc pin (v cca and v ccy ) should be bypassed using low effective series resistance (esr) and effective series inductance (esi) capacitors placed as close as possible to the v cca and v ccy pins. the parasitic induc- tance of the high speed signal track can cause significant overshoot. this effect can be reduced by keeping the length of the tracks as short as possible. a solid copper plane for the return path (gnd) is also recommended.
adg3308/ADG3308-1 rev. c | page 19 of 20 outline dimensions compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarit y 0.10 figure 42. 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters 3.75 bcs sq 4.00 bsc sq compliant to jedec standards mo-220-vggd-1 082207-b 1 0.50 bsc p i n 1 i n d i c a t o r 0.75 0.60 0.50 top view 12 max 0.80 max 0.65 typ seating plane pin 1 indi c ator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 2.25 2.10 sq 1.95 20 6 16 10 11 15 5 exposed pad (bottom view) 0.60 max 0.60 max 0.25 min figure 43. 20-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-20-1) dimensions shown in millimeters
adg3308/ADG3308-1 rev. c | page 20 of 20 070606- a a 1 23 4 b c d bottom view (ball side up) top view (ball side down) e 2.06 2.00 1.94 2.56 2.50 2.44 a1 ball identifier 0.65 0.59 0.53 0.28 0.24 0.20 0.36 0.32 0.28 0.50 bsc pitch figure 44. 20-ball wafer level chip scale package [wlcsp] (cb-20-2) dimensions shown in millimeters 0 81707-b a 1 23 4 b c d bottom view (ball side up) top view (ball side down) e 2.06 2.00 1.94 2.56 2.50 2.44 a1 ball identifier 0.28 0.24 0.20 0.36 0.32 0.28 0.50 bsc pitch 0.042 0.040 0.037 0.645 0.585 0.525 figure 45. backside-coated 20-ball wafer level chip scale package [wlcsp] (cb-20-3) dimensions shown in millimeters ordering guide model temperature range package description package option adg3308bruz 1 ?40c to +85c 20-lead thin shrink small outline package [tssop] ru-20 adg3308bruz-reel 1 ?40c to +85c 20-lead thin shrink small outline package [tssop] ru-20 adg3308bruz-reel7 1 ?40c to +85c 20-lead thin shrink small outline package [tssop] ru-20 adg3308bcpz-reel 1 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adg3308bcpz-reel7 1 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adg3308bcbz-1-rl7 1 ?40c to +85c 20-ball wafer level chip scale package [wlcsp] cb-20-2 adg3308bcbz-1-reel 1 ?40c to +85c 20-ball wafer level chip scale package [wlcsp] cb-20-2 adg3308bcbz-2-rl7 1 ?40c to +85c backside-coated 20-ball wafer level chip scale package [wlcsp] cb-20-3 adg3308bcbz-2-reel 1 ?40c to +85c backside-coated 20-ball wafer level chip scale package [wlcsp] cb-20-3 t 1 z = rohs compliant part. ?2005C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04865-0- 9 /07(c) ttt

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